Ran Ginosar
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Associate Professor, Department of Electrical Engineering and Department of Computer Science Head, VLSI Systems Research Center Member, Advanced Circuit Research Center Technion-Israel Institute of Technology Haifa 32000, Israel Office: EE 904 Phone: +972-4-829-4645 Cell: +972-528-700-580 Fax: +972-4-829-5757 Email: ran at ee.technion.ac.il BSc (scl), Technion, 1978; PhD, EECS, Princeton University, 1982 |
Neurochips
The Neuroprocessor book VLSI Architecture:
Network-on-Chip and Chip Multi-Processors
Many-Core Architecture following the PRAM paradigm
Rad-Safe VLSI for Space ApplicationsAsynchronous VLSI:
Synchronization and Multi-Clock Domains (MCD) Systems on Chip (SOC)
Asynchronous design
Shlomo Beer (PhD): Advanced Synchronizer Circuits
Efi Rotem (PhD): Multiple Clock Domain Chips (co-advisors Uri Weiser and Avi Mendelson).
Dmitry Vainbrand (MSc): NoC for Neural Network Processors
Ameer Abdel-Hadi (MSc): Non-uniform Mesh clocking (co-advisors Avinoam Kolodny and Eby Friedman)
Shimon Manor (MSc): Low Power Multisynchronous Clocking
Danniel Nahmanny (MSc): High Speed Communication Circuits
Eyal Friedman (MSc): Processor-to-Memory NoC in Many-core Architecture
Dmitri Khoretz (MSc): Memory Performance in Many-core Architecture
Industrial Involvement and Entrepreneurship
Last Update: 04/01/2010
